Seminare und Vorträge 2025
Übersicht über alle zukünftigen IPP-Seminare, -Kolloquien und Vorträge

Übersicht über alle zukünftigen IPP-Seminare, -Kolloquien und Vorträge


Ort: L6 II

EPS Rehearsals

AUG Seminar

From concept to first coil of STAR_Lite a university-scale Stellarator for training and research

AUG Seminar
STAR_Lite, a university-scale stellarator under development at Hampton University, is a student-driven initiative designed to provide unparalleled hands-on training in fusion science and contribute to cutting-edge stellarator research, particularly in areas like non-resonant divertors. This presentation provides an update on the significant progress achieved over the past year, charting the journey from initial conceptualization to the fabrication of the first modular coil. Key developments include a strategic design pivot from an initial helical concept to the computationally optimized QUASR 104183 configuration, and the implementation of an innovative 'spine winding' technique for in-house coil manufacturing. We will highlight the integral role of undergraduate and high school students in various aspects of the project, including power system development, prototype construction (STAR_little), and theoretical studies. The talk will detail the challenges overcome, the lessons learned, and the current status of STAR_Lite as it moves towards becoming an operational research and educational platform, underscoring the viability of impactful, student-led fusion projects at the university level. [mehr]

EPS Rehearsals

AUG Seminar

EPS Rehearsal

AUG Seminar
Bernhard Sieglin - First experiments on alternative divertor configurations in ASDEX~Upgrade [mehr]

Evaluation of the Teledyne ADQ32 Card for Thomson Scattering Diagnostics

AUG Seminar
Teledyne SP Devices has developed high-performance data acquisition systems that integrate an open FPGA to enable real-time signal processing. This work explores the feasibility of implementing the Thomson scattering dispersion algorithm directly on the FPGA of theADQ32 digitizer. The algorithm was developed using high-level synthesis (HLS), while a hardware description language (HDL) was used to interface with the ADQ signal architecture. A dedicated control program was built within the Discharge Control System (DCS), leveraging the API provided by Teledyne to configure and operate the card. The FPGA-based implementation produced results identical to the C++ version of the algorithm, with an execution time of 170μs, demonstrating its potential for real-time plasma diagnostics. [mehr]
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